Ayoub Sadeghi

J1. An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications.

Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Dr. Nabiollah Shiri.

Microelectronics Journal, 2021, https://doi.org/10.1016/j.mejo.2021.105287.

Different digital multipliers have resulted from various algorithms and hardware designs. This article presents a high-performance multiplier by a novel AND gate and a modified hybrid full adder (FA) cell. The AND is designed by using the pass transistor logic (PTL) technique and a speed-up transistor, while the FA is based on the transmission gate (TG). Low-power, high-speed, low power-delay-product (PDP), and high competency of both circuits for using in sophisticated structures like multipliers are confirmed by mathematical relations. The proposed 4-bit array multiplier circuit along with the pad has a 2.87 mm² total area and is investigated under different circumstances including VDD, frequency, load capacitances, and process-voltage-temperature (PVT) variations using Monte Carlo method (MCM) by HSPICE tool and 90 nm technology. The efficiency of the multiplier in image processing applications is proved with average improvements of 12.61% and 32.045% for peak signal-to-noise ratio (PSNR) and PDP compared to state-of-the-art designs, respectively. The overall results of the multiplier approve its capability for digital signal processors (DSPs).

J2. High-Performance 1-Bit Full Adder with Excellent Driving Capability for Multistage Structures.

Mahmood Rafiee, Dr. Nabiollah Shiri, Ayoub Sadeghi.

IEEE Embedded Systems Letters, August 2021, doi: 10.1109/LES.2021.3108474.

In this brief, a low-power 1-bit full adder (FA) cell is proposed based on the transmission gate (TG) to attain a special module for generating full swing Carry output. The cell benefits from the high driving capability for both Sum and Carry outputs when embedding in multistage structures like ripple carry adders (RCAs), compressors, and multipliers. The proposed TG-based FA has a total die area of 60.02 μm2, while the average power, delay, and power-delay-product (PDP) are 10.829 μW, 3.1954 ns, and 34.603 fJ, respectively. The results introduce the FA cell as an efficient gate for integrated circuits (ICs).

J3. An approximate CNTFET 4:2 compressor based on gate diffusion input and dynamic threshold.

Mahmood Rafiee, Yaqhoub Sadeghi, Dr. Nabiollah Shiri,Ayoub Sadeghi.

Electronic Letter, 57: 650-652, 2021, https://doi.org/10.1049/ell2.12221.

In this paper, a new 4:2 approximate compressor is presented by the gate diffusion input (GDI) technique. Although GDI cells suffer from threshold voltage drop, the dynamic threshold (DT) approach and carbon nanotube field-effect transistors (CNTFETs) are merged to overcome the mentioned problem. The proposed cell has full-swing outputs, while its error and power delay product (PDP) are at low rates. Low voltage multipliers that are used in image processing can benefit from the proposed compressor.

J4. Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications.

Ayoub Sadeghi, Dr. Nabiollah Shiri, Mahmood Rafiee.

Circuits, Systems, and Signal Processing, 39, 6247–6275, 2020, https://doi.org/10.1007/s00034-020-01459-x.

Size reduction in complementary metal–oxide–semiconductor integrated circuits (ICs) is a challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages such as low power, high mobility, and ballistic transmissions is an alternative. Based on the standard 32 nm CNTFET technology, a new 23-transistor full adder cell is proposed with combining advantages of gate diffusion input and transmission gate techniques, which are low power and full swing. Owing to small number of transistors and internal nodes, the delay time and activity factor decreased to 13.5τ. Simulations of critical parameters variations like VDD, temperature, and fan-out expose better performance of the proposed cell. Investigating the process voltage temperature with Monte Carlo simulation verified better stability, immunity, and tolerability of the cell in comparison with well-known full adder cells. Suggested full adder cell was implemented in 4:2 compressor with 9.0298 fJ of power delay product and minimum area occupation among the references. Based on real chip measurements, total die area occupation for proposed full adder and compressor is 0.505 µm2 and 1.092 µm2, respectively. Proposed circuits were applied to an 8-bit subtractor for orthopantomogram image processing to detect tooth core build up and restored with dental filling in order to maintain a crown restoration. Merits of proposed circuits both in IC design and image processing make these circuits suitable choice for bioelectronics chips.

J5. A low-power pseudo-dynamic full adder cell for image addition.

Ayoub Sadeghi, Dr. Nabiollah Shiri, Mahmood Rafiee, Parisa Rahimi.

Computers & Electrical Engineering, Volume 87, 2020, https://doi.org/10.1016/j.compeleceng.2020.106787.

Integrated circuits (ICs) employ static and dynamic logic to improve performance and scalability. This paper presents a new circuit design approach named pseudo-dynamic logic (PDL), which shows the advantages of both static and dynamic cells. The PDL is evaluated by using a new full adder cell with 18 transistors. In the presented full adder, gate diffusion input (GDI), transmission gate (TG), and float techniques are combined, and pull-up or pull-down networks are changed into a new configuration so that the number of transistors and internal nodes will decrease. Post-layout simulations and digital image addition are performed to evaluate the real environment and practical application of the cell. Peak signal to noise ratio (PSNR), mean square error (MSE), and structural similarity index metric (SSIM) are calculated to study the cell performance in image processing. Compared to the dynamic and static circuits, the proposed PDL-based full adder cell performs better, and the results validate its effectiveness.

J6. Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II.

Ebrahim Abiri, Abdolreza Darabi, Mohammad Reza Salehi, Ayoub Sadeghi.

Circuits, Systems, and Signal Processing, 39, 4516–4551, 2020, https://doi.org/10.1007/s00034-020-01382-1.

Gate-diffusion input (GDI) method using a simple cell, makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nano-tube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nano-scales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm-II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits (FOMs) in worst-case delay, and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using and a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte-Carlo procedure in standard 32nm technology utilizing the Synopsys H-SPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible based applications, such as future generations of FPGA chips and CNTFET-based computers.

J7. Gate-diffusion input (GDI) method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems.

Ebrahim Abiri, Abdolreza Darabi, Ayoub Sadeghi.

Microelectronics Journal, Volume 87, Pages 81-100, 2019, https://doi.org/10.1016/j.mejo.2019.04.001.

In this work, CNTFET-based GDI (CNT-GDI) and QCA-based GDI (QCA-GDI) methods (CNT/QCA-GDI) for designing unique ultra-efficient analogue and logical blocks in voltage-mode fuzzy and quantum systems are presented. Extensive Monte-Carlo simulations by using Synopsys H-SPICE simulator at 16 nm technology demonstrate that the analogue blocks improve considerably in term of performance, absolute error and energy consumption in the presence of compact variations in compared to their counterparts. Also, the logical blocks have advantages including fast response, high polarity and lower power-consumption achieved by the QCADesigner and QCAPro tools at 18 nm in contrast to the similar designs. As applications, the half wave rectifier (HWR) and full-wave rectifier (FWR) by employing the proposed methods in two technologies are implemented. The results show improvement for the proposed circuits with correct function and very high robustness under major variations in contrast to state-of-the art rectifier architectures at similar conditions. Consequently, the proposed methods are appropriate for designing integrated circuits (ICs) with higher capacity and energy-efficient for the emerging nano-technologies.

C1. An Ultra Efficient and Reliable TG-PTL Based Full Adder Cell.

Ayoub Sadeghi, Dr. Nabiollah Shiri.

The 5th International Conference on the New Horizons in the Electrical Engineering, Computer and Mechanical. Tehran, Iran, May 2020.

In this paper by using particular features of transmission gate (TG) and pass transistor logic (PTL) techniques a new full adder cell with 16 transistors proposed and investigated. Owing to used techniques, low number of transistors required which leads to low number of internal nodes and parasitic capacitances. As privileges of the proposed cell, ultra-low power consumption, high speed and performance and low energy dissipation based on small area occupation can be named. Extensive simulations such as power supply, frequency, load capacitance and temperature along with process variations applied. Accuracy and robustness of the proposed cell versus mentioned circumstances confirmed its ability for being used in next future generation of integrated circuits.

C2. Tolerance Binary Comparator with Ultra-Power Saving Capability Based on Transmission Gate (TG) Technique.

Ayoub Sadeghi, Dr. Nabiollah Shiri.

4th International Conference on Electrical Engineering, Computer Science and Information Technology, Hamadan, Iran, February 2020.

In this paper a new magnitude comparator based on transmission gate (TG) technique with 14 transistors is presented. The proposed circuit due to special feature of used technique has low resistivity, internal nodes and internal diffusion and parasitic capacitances. These characteristics drives the circuit with ultra-low power consumption, short paths from inputs to output for achieving high speed rate and finally high PDP dissipation savings. Various simulations using 90nm CMOS technology including VDD, frequency, temperature and load capacitances applied. Also, investigations in term of process corners and possible fabrication process using Monte Carlo performed. Attained results indicated the proposed circuit stability, tolerability, efficiency and low sensitivity to variations under different circumstances such as process voltage temperature (PVT), gate oxide thickness (tox) and diffusion doping concentration (NSD) variations. All attainment suggest the proposed circuit as an appropriate selection for being used in more sophisticated chips for future generation application.

C3. Small Area GDI Based Single Bit Magnitude Comparator with Low Power and High Speed.

Ayoub Sadeghi, Dr. Nabiollah Shiri.

4th Conference on Electrical Engineering, Mechanical Engineering, Computer Science and Engineering, Delhi, India, January 2020.

In this paper with focusing on the most important parameter in dynamic power consumption, area occupation reduction, a new 1-bit magnitude comparator with only 11 transistors and non-use of any inverters in inputs is presented. Low internal nodes and consequently low internal parasitic and diffusion capacitances provided the proposed circuit with high efficiency in term of power, speed and energy saving. Extensive simulations regarding dynamic power consumption such as power supply, frequency, load capacitance and temperature accomplished. Also, in term of Process Voltage Temperature (PVT) variations Monte Carlo used with standard deviations. All attained results under various and diverse circumstances proved the superiority of the proposed circuit in term of PDP consumption compared to its state of the art designs. Hence, high reliability and practicability of the proposed circuit nominated it as an adequate alternative to conventional designs for being utilized in different applications such as image processing.

S1. Ayoub Sadeghi, Dr. Nabiollah Shiri, Mahmood Rafiee, Abdolreza Darabi, Ebrahim Abiri, "Voltage Over-Scaling CNT-Based 8-Bit Multiplier by Low-Threshold GDI-Based Counters". Integration the VLSI Journal, Sep. 2021.

S2. Ayoub Sadeghi, Mahmood Rafiee, Dr. Nabiollah Shiri, Mahsa Tahghigh, "An efficient counter-based Wallace-tree multiplier with hybrid full adder core for image blending". Frontiers of Information Technology & Electronic Engineering, Sep. 2021.

S3. Mahmood Rafiee, Dr. Nabiollah Shiri, Ayoub Sadeghi, Abdolreza Darabi, Ebrahim Abiri, "Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing" Circuits, Systems, and Signal Processing (in revision stage).

S4. Dr. Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, Maryam Bigonah, "SR-GDI CNTFET-Based Magnitude Comparator for New Generation Programmable Integrated Circuits". International Journal of Circuit Theory and Applications, August 2021 (in revision stage).

S5. Ayoub Sadeghi, Dr. Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour, "Tolerant and Low Power Subtractor with 4:2 Compressor and a New TG-PTL-Float Full Adder Cell". Microelectronics Journal, October 2021.

S6. Dr. Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, "High-Efficient and Error-Resilient GDI-Based Approximate Full Adders for Complex Multistage Rapid Structures". Computers & Electrical Engineering, May 2021.